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Page last modified 15:09, 10 Aug 2011 by stephan

User Manual for Zefant-nanoV4

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    The Zefant-nanoV4 is a small but extremely powerful FPGA module. On 49mm x 39mm you get a complete high end Xilinx Virtex-4 based FPGA solution.

    It contains Virtex-4 FX or LX FPGA, DDR2 memory, flash memory, wide range power supply and much more on a high end impedance controlled 12 layer PCB. You only need a single power supply (5...12V) to run the module, everything else is already integrated.

    Compared to the old nano-3E modules additional pins are available (100 pins per connector instead of 80), but the old connectors can optionally be occupied as well for backwards compatibility. With the new connectors the pinout has been improved a lot, more free I/Os, more differential pairs and additional physical layer pins.

    The module can be used together with the Zemu-nano Microcontroller modules, these fit on top of the module. The first "nano Universal Baseboard" is already prepared for the use of a stack of these modules as well.

    Hardware Description


    The main elements of the module are shown in the system block diagram:


    The CPLD by default is only used for configuration of the FPGA. Most pins of the connectors on top and bottom side are routed through 1:1.

    JTAG  Chain

    Generally the JTAG chain contains 2 devices: The Virtex-4 FX12/LX25 (Device 1) and the Coolrunner2 CPLD (Device 2).


    Since the CPLD configures all dedicated signals of the FPGA it is generally possible to lock yourself out of the JTAG chain, because the FPGA doesn't enable JTAG if it's still in reset mode. So, for the case of a wrong CPLD configuration there is the possibility to take the FPGA out of the JTAG chain to allow for reprogramming the CPLD under any circumstances. Please refer to the solder bridge description.

    Solder Bridges

    Solder Bridge Descriptions

    The module contains 5 solder bridges in total, all of which are located on the bottom PCB side:



    Solder Bridge Signals Description
    SB301 Pad 1: JTAG TDI
    Pad 2: FPGA TDI
    Connect FPGA TDI to JTAG TDI
    SB302 Pad 1: FPGA TDO
    Pad 2: CPLD TDI
    Pad 3: JTAG TDI
    Select CPLD TDI from JTAG TDI or FPGA TDO
    SB901 Pad 1: VCC33
    Pad 2: VCCIO248
    Connect VCCIO248 to VCC33
    Remove this to use a different I/O voltage on I/O banks 2,4 and 8
    SB902 Pad 1: VCC33
    Pad 2: VCCIO16
    Connect VCCIO16 to VCC33
    Remove this to use a different I/O voltage on I/O banks 1 and 6
    SB903 Pad 1: JTAG TDI
    Pad 2: FPGA TDI
    Remove this for stacked modules

    For identification Pad#1 is larger than the other pad(s) and is marked by broken outline.

    Default Solder Bridge Settings

    With the default setting of the solder bridges, the JTAG chain contains both devices, FPGA and CPLD:

    Solder Bridge Default Description
    SB301 Set FPGA TDI connected to JTAG TDI
    SB302 Set to 1-2 CPLD TDI connected to FPGA TDO
    SB901 Set VCCIO248 fixed to VCC33
    SB902 Set VCCIO16 fixed to VCC33
    SB903 Set JTAG conected TDO to JTAG BYPASS

    "CPLD only" Solder Bridge Settings

    If the solder bridges are set like this, the CPLD chain contains only the CPLD. The FPGA is not in the chain anymore:

    Solder Bridge Default Description
    SB301 Open FPGA TDI not connected
    SB302 Set to 2-3 CPLD TDI connected directly to JTAG TDI

    Use this configuration if the FPGA cannot boot anymore due to bad CPLD configuration.


    A total of 2 oscillators can be occupied on the module:

     Part  PCB Side
     Signal Name
     G601  top  100MHz  clk100
     G602  bottom  not occupied by default  osc2

    G601 is connected to FPGA and CPLD, G602 is connected to FPGA only.

    If you want to add or exchange an oscillator you can use virtually any 3.3V oscillator with dimensions of 5x3.2mm. You can use a MEMS or standard oscillators, example for standard oscillator would be Abracon ASFL1 series, example for MEMS could be Abracon ASFLM1. But any other oscillator of this size will work as well.

    Please note orientation and pinout of the oscillators:

    G601 on top PCB side:


    G602 on bottom PCB side:


    BTB Connectors

    Connector Types

    The Board-to-Board connectors are Hirose FX10A types:

      Connector on Module
    Mating Connector
    Top FX10A-100S/10-SV(xx) FX10A-100P/10-SV1(xx)
    Bottom FX10A-100P/10-SV1(xx) FX10A-100S/10-SV(xx)

    Board stacking height is 5mm.

    A datasheet for the connectors can be downloaded here from Hirose.

    Pin Numbering

    The pins of the BTB connectors are numbered as shown in the following photos. On the PCB pin 1 is identified by a bevelled corner on the connector.

    Top PCB side:


    Bottom PCB side:



    Short notes for special or dedicated signals:

    Signal Name
    Signal Type
    VIN Power Power supply input
    4.5V ... 15V are allowed here.
    High voltage versions up to 35V on special request.
    VCC33 Power 3.3V output
    Depending on the FPGA code, the onboard power supply can deliver up to ~0.8A to your application board. With high I/O frequencies this available current can be lower.
    VCCIO248 Power I/O voltage for banks 2, 4 and 8
    If jumpered on the module, this delivers 3.3V
    If not jumpered on the module, you have to connect your desired I/O voltage here for banks 2, 4 and 8.
    VCCIO16 Power

    I/O voltage for banks 1 and 6
    If jumpered on the module, this delivers 3.3V
    If not jumpered on the module, you have to connect your desired I/O voltage here for banks 1 and 6.


    These pins do only route the top connector down to the bottom connector, to allow for direct PHY connections of modules plugged onto the Zefant.

    They are not connected to any circuitry on the module.


    These signals are shared with the CPLD and are normally required when programming the flash memory.
    Generally they can be used like free I/Os but don't forget to check what your CPLD code does on these I/Os and be aware that (regarding signal integrity) they have stub traces to the CPLD and may not be the best choice for highest I/O frequencies.


    These signals do are only single ended, because the according "P" signals are connected to the onboard oscillators.

    These pins are not shared with anything else, just be aware that you cannot connect a differential pair here.

    FIO_x_Lyy_z IO

    These are completely free I/Os
    x = Bank number
    yy = differential pair number
    z = (P)ositive / (N)egative
    Be aware that on the connector the P/N order is not always alternating but differs from pair to pair! (to safe unnecessary vias for better signal integrity)

    These pins are not shared with anything else, you can use them freely, except for the pairs mentioned in the previous row of this table.

    Bank I/O Voltages

    Bank No.
    Power Supply Signal Name
    0 (Dedicated IO) VCC33 3.3V fixed
    1 VCCIO16 externally supplied or 3.3V
    connected to bank 1 and 6
    2 VCCIO248 externally supplied or 3.3V
    connected to bank 2,4,8
    3 VCC33 3.3V fixed
    4 VCCIO248 externally supplied or 3.3V
    connected to bank 2,4,8
    5 VCC18 1.8V fixed (DDR2 memory)
    6 VCCIO16 externally supplied or 3.3V
    connected to bank 1 and 6
    7 VCC18 1.8V fixed (DDR2 memory)
    8 VCCIO248 externally supplied or 3.3V
    connected to bank 2,4,8


    Mechanical Dimensions

    The major dimensions of the module are 49 x 39mm.


    The stacking height is 5mm (board to board distance). Optionally different connectors could be used for 4mm stacking height.

    Technical Data


    Order Number ZNANO-V4FX ZNANO-V4LX
    FPGA Virtex4-FX12
    CPLD Coolrunner2
    RAM  2x 512MBit = 128MByte / 32bit
    (optional 2x 1GBit / 256MByte on special request)
    Flash 64MBit Serial Flash
    FPGA Configuration from JTAG, Serial Flash, from Baseboard through CPLD
    Oscillators, Clock Standard: 100MHz
    additional second oscillator on request
    multiple external clock inputs available
    Connectors 4x Hirose FX10A / 100pin
    User Interface 1 pushbutton
    3 LEDs
    misc. solder bridges
    Integrated Power Supply 3 DC/DC converters: 1.2V, 1.8V, 3.3V
    2 LDOs: 0.9V, 2.5V
    External I/O

    152 free I/Os:
    "North" connector: 74 I/Os, 34 diff. pairs
    "South" connector: 78 I/Os (8 shared with CPLD), 35 diff. pairs (31 without stubs)

    I/O voltages 2 externally supplied bank voltages plus 3.3V can be used simultaneously
    Mechanical Dimensions 49 x 39mm
    Stacking Height 5mm
    Power Supply Voltage Range 4 ... 15V
    Power Dissipation Minimal Design: 0.5W
    DDR2 Controller Example Design w/ full termination: 2.2W

    Software and Resources


    All resources and software downloads for the Zefant-nanoV4 can be downloaded from the subversion repository. You can access the repository here:

    GForge Repository Web Frontend Access
    Public Repository Access with Subversion client*
    Customer Repository Access with Subversion client*
    Repository Access with ViewVC Web Frontend

    * like Tortoise for example.

    Repository Hierarchy

    The most important directories of the repository will be mentioned in this incomplete list. It will pay out to browse the repository by yourself!

    trunk/Software/_common Pin constraints files (.UCF files) for CPLD and FPGA on Zefant-nano V4
    trunk/Software/cpld_blinky Simple blinking example for CPLD
    trunk/Software/fpga_blinky Simple blinking example for FPGA
    trunk/Software/cpld_simple_config Minimalistic CPLD configuration (to serve as an example for configuration of the FPGA dedicated pins)

    DDR2 memory controller generated by Xilinx CoreGenerator.
    This implementation is configured only 8 bits wide and 4 bitfiles for each of the four 8bit lanes is available for both modules (FX12/LX25). In case of hardware problems, this can help detecting in which byte lane the problem exists.

    trunk/Software/mem_test_32bit DDR2 memory controller generated by Xilinx CoreGenerator
    This implementation is configured 32 bits wide and can serve as an example for production designs.
    trunk/Software/spi_flasher Flash Programmer Application for onboard SPI Flash
    This is compatible with the Windows FlashProg_GUI and allows programming and reading out the flash chip
    trunk/Software/cpld_boot_config CPLD configuration that configures the FPGA from SPI flash after power-up.

    Additional Files in external Repositories


    Repository Links Description
    flashprog-win Project Overview Windows GUI for spi_flasher
    for programming the onboard SPI flash easily with a windows user interface over USB / RS232 connection
    SVN Access
    Wiki Documentation
      Project Overview    
    SVN Access  
    Wiki Documentation  

    Options and Patches in Hardware

    During the life of a product customers have may have asked for some features which were not planned originally. In this chapter we want to share these requests and how they have been solved.

    SelectMAP Support

    Originally we were planning to support serial configuration on this module only and not use SelectMAP at all. However, due to a customer request, we want to show, how to enable it easily anyway. I requires only 2 additional wires on the module as show in the photo:


    The wires connect the two dedicated FPGA signals FPGA_RDWR# and FPGA_CS# with free pins of the CPLD as shown in the table:

     Signal  CPLD Pin
     FPGA Pin
     FPGA_RDWR#  7  F9
     FPGA_CS#  5  E8

    When reproducing this patch, it is recommended to use these CPLD pins, because in a futere PCB version, this change will be included with this pinout.

    With this patch applied, you have all required signals available on the CPLD and BTB connectors, to support SelectMAP configuration of the FPGA from a baseboard.

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    Zefant-nanoV4 Mechanical Dimensions
    20.61 kB09:57, 18 Jun 2009stephanActions
    Zefant-nanoV4 JTAG Chain
    4.1 kB19:19, 15 Aug 2009stephanActions
    G602 Oscillator Pinout (Bottom PCB Side)
    30.95 kB11:43, 7 Dec 2010stephanActions
    G601 Oscillator Pinout (Top PCB Side)
    32.81 kB11:43, 7 Dec 2010stephanActions
    Zefant nano V4 SelectMAP Patch
    430.7 kB15:23, 15 Apr 2011stephanActions
    Zefant nanoV4 Pin Numbering Bottom Side
    187.32 kB20:43, 25 Jun 2011stephanActions
    Zefant nanoV4 Pin Numbering Top Side
    168.16 kB20:43, 25 Jun 2011stephanActions
    Zefant-nano V4 Solder Bridges
    175.35 kB14:39, 22 Sep 2010stephanActions
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