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Wiki > English > Products > FPGA Modules > Zefant-nano > Zefant-nano (Virtex 4) > User Manual for Zefant-nanoV4
User Manual for Zefant-nanoV4From $1Table of contents
IntroductionThe Zefant-nanoV4 is a small but extremely powerful FPGA module. On 49mm x 39mm you get a complete high end Xilinx Virtex-4 based FPGA solution. It contains Virtex-4 FX or LX FPGA, DDR2 memory, flash memory, wide range power supply and much more on a high end impedance controlled 12 layer PCB. You only need a single power supply (5...12V) to run the module, everything else is already integrated. Compared to the old nano-3E modules additional pins are available (100 pins per connector instead of 80), but the old connectors can optionally be occupied as well for backwards compatibility. With the new connectors the pinout has been improved a lot, more free I/Os, more differential pairs and additional physical layer pins. The module can be used together with the Zemu-nano Microcontroller modules, these fit on top of the module. The first "nano Universal Baseboard" is already prepared for the use of a stack of these modules as well.
Hardware DescriptionOverviewThe main elements of the module are shown in the system block diagram:
The CPLD by default is only used for configuration of the FPGA. Most pins of the connectors on top and bottom side are routed through 1:1. JTAG ChainGenerally the JTAG chain contains 2 devices: The Virtex-4 FX12/LX25 (Device 1) and the Coolrunner2 CPLD (Device 2).
Since the CPLD configures all dedicated signals of the FPGA it is generally possible to lock yourself out of the JTAG chain, because the FPGA doesn't enable JTAG if it's still in reset mode. So, for the case of a wrong CPLD configuration there is the possibility to take the FPGA out of the JTAG chain to allow for reprogramming the CPLD under any circumstances. Please refer to the solder bridge description.
Solder BridgesSolder Bridge DescriptionsThe module contains 5 solder bridges in total, all of which are located on the bottom PCB side:
For identification Pad#1 is larger than the other pad(s) and is marked by broken outline. Default Solder Bridge SettingsWith the default setting of the solder bridges, the JTAG chain contains both devices, FPGA and CPLD:
"CPLD only" Solder Bridge SettingsIf the solder bridges are set like this, the CPLD chain contains only the CPLD. The FPGA is not in the chain anymore:
Use this configuration if the FPGA cannot boot anymore due to bad CPLD configuration.
OscillatorsA total of 2 oscillators can be occupied on the module:
G601 is connected to FPGA and CPLD, G602 is connected to FPGA only. If you want to add or exchange an oscillator you can use virtually any 3.3V oscillator with dimensions of 5x3.2mm. You can use a MEMS or standard oscillators, example for standard oscillator would be Abracon ASFL1 series, example for MEMS could be Abracon ASFLM1. But any other oscillator of this size will work as well. Please note orientation and pinout of the oscillators: G601 on top PCB side:
G602 on bottom PCB side:
BTB ConnectorsConnector TypesThe Board-to-Board connectors are Hirose FX10A types:
Board stacking height is 5mm. A datasheet for the connectors can be downloaded here from Hirose. Pin NumberingThe pins of the BTB connectors are numbered as shown in the following photos. On the PCB pin 1 is identified by a bevelled corner on the connector. Top PCB side:
Bottom PCB side:
SignalsShort notes for special or dedicated signals:
Bank I/O Voltages
Mechanical DimensionsThe major dimensions of the module are 49 x 39mm. The stacking height is 5mm (board to board distance). Optionally different connectors could be used for 4mm stacking height.
Technical Data
Software and ResourcesLinksAll resources and software downloads for the Zefant-nanoV4 can be downloaded from the subversion repository. You can access the repository here:
* like Tortoise for example. Repository HierarchyThe most important directories of the repository will be mentioned in this incomplete list. It will pay out to browse the repository by yourself!
Additional Files in external Repositories
Options and Patches in HardwareDuring the life of a product customers have may have asked for some features which were not planned originally. In this chapter we want to share these requests and how they have been solved. SelectMAP SupportOriginally we were planning to support serial configuration on this module only and not use SelectMAP at all. However, due to a customer request, we want to show, how to enable it easily anyway. I requires only 2 additional wires on the module as show in the photo:
The wires connect the two dedicated FPGA signals FPGA_RDWR# and FPGA_CS# with free pins of the CPLD as shown in the table:
When reproducing this patch, it is recommended to use these CPLD pins, because in a futere PCB version, this change will be included with this pinout. With this patch applied, you have all required signals available on the CPLD and BTB connectors, to support SelectMAP configuration of the FPGA from a baseboard.
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